This answer record contains the Release Notes and Known Issues for System Generator for DSP 2014.2.
Installation instructions and a list of the Release Notes and Known Issues in System Generator for DSP 2014.2 tools are included in this answer record.
A successful installation of Vivado Design Suite 2014.2 changes your design tools version number to 2014.2.
Release Notes and New Features in System Generator for DSP 2014.2
For a list and description of the new features and Release Notes in the 2014.2 tools, see the Vivado Design Suite User Guide - Release Notes, Installation and Licensing (UG973)
Please be sure to read the documentation because it answers questions that you might have about changes to the functionality or the look-and-feel from previous versions of System Generator for DSP.
The Vivado Design Suite User Guide - Model-Based DSP Design using System Generator is accessible in PDF format at:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug897-vivado-sysgen-user.pdf.
For System Generator for DSP Release Notes for other versions, see (Xilinx Answer 29595).
Note: For Vivado Design Suite Model Based DSP Design using System Generator from 2013.1 and supported OS and MATLAB versions, please see (Xilinx Answer 55830).
General
| (Xilinx Answer 53806) | Vivado System Generator - How can I use the legacy designs in Vivado Sysgen? |
| (Xilinx Answer 52571) | Vivado System Generator - Does Vivado SysGen use CoreGen or IP Catalog in the backend? |
| (Xilinx Answer 47623) | Vivado DSP Tools - System Generator for DSP 2012.1 - Why do I get critical warnings on pin locations and constraints not applied for a model in a design with multiple unique SysGen submodules? |
| (Xilinx Answer 52330) | Vivado System Generator - How do I configure MATLAB with Vivado System Generator? |
| (Xilinx Answer 58441) | System generator for DSP 2013.3 -xlTimingAnalysis error |
| (Xilinx Answer 58175) | 2013.3 SysGen - IP Packager flow does not provide zipped packaged IP |
| (Xilinx Answer 60311) | Vivado System Generator - When does Vivado System Generator check out the license? |
Resolved Issues
| (Xilinx Answer 60552) | Vivado System Generator - Cannot create a Hardware Co-Simulation library block for a Subsystem in my model |
| (Xilinx Answer 60617) | 2014.1 Vivado System Generator - Closing a Xilinx Blockset block GUI using the "X" in the top right corner of the GUI can cause the block GUI to hang |
| (Xilinx Answer 60187) | 2014.1 System Generator - Waveform Viewer displays the incorrect clock period in multi-clock domain designs |
Known Issues
| (Xilinx Answer 62185) | 2014.2 Vivado System Generator - Cannot generate a design on some Kintex or Virtex UltraScale devices from the System Generator token |
| (Xilinx Answer 62097) | 2014.2 SysGen - CORDIC v6.0 instance causes incorrect behavior elsewhere in model |
| (Xilinx Answer 62328) | Vivado Sysgen - When MYVIVADO environment variable is set, Vivado Sysgen can produce errors when trying to open and modify Xilinx blocks or the Sysgen token |
| (Xilinx Answer 62096) | 2014.2 SysGen - Too many clocks generated in a multi-clock domain design |
| (Xilinx Answer 61003) | 2014.1 Vivado Sysgen - ModelSim block produces an STL library error loading librdi_sysgen_mti_fli_controller.so |
| (Xilinx Answer 59236) | 2014.1 System Generator - Sysgen/Matlab library compatibility issues may occur with Sysgen 2014.1 on Linux OS |
| (Xilinx Answer 58837) | 2013.3 Vivado SysGen - ModelSim block produces errors in ModelSim console: can't read "vsimPriv(windowmgr)": no such element in array / # ** Error: Tree does not exist |
| (Xilinx Answer 58569) | Vivado 2013.3 SysGen - Unable to make recursive copy for the .mdl file |
| (Xilinx Answer 58836) | 2013.3 Vivado Sysgen - Blackbox block failing behavioral simulation with Data Mismatches for both VHDL and Verilog |
| (Xilinx Answer 56042) | 2013.1 Vivado System Generator - Migrating from Vivado 2012.4 to 2013.1 will lead to different pinout on the HDL generated, no CE pin created in 2013.1 |
| (Xilinx Answer 53961) | Vivado SysGen - Several synthesis errors occur when using the IP Packager flow in Vivado if the path length exceeds 256 characters |
| (Xilinx Answer 57604) | Why is the fractional width on the "reload_tdata_data" port no longer dynamic in the FIR Compiler? |
| AR# 60959 | |
|---|---|
| 日期 | 10/01/2015 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |