ERROR : Memory interface signals should be selected in consecutive banks. Banks selected: 9, 11, 10.
To bypass this error and proceed further for design generation, refer to AR #43481.
INFO : Cannot verify further unless the existing errors are resolved.
Revision History
06/09/2014 - Initial Release
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
54025 | MIG 7 Series - IP Release Notes and Known Issues for Vivado | N/A | N/A |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
43481 | MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Verify UCF fails with new bank selection rules | N/A | N/A |
AR# 60958 | |
---|---|
日期 | 06/06/2014 |
状态 | Active |
Type | 已知问题 |
器件 | |
IP |