描述
My design has two FIFO_SYNC_MACRO instances declared via the COMPONENT declaration in VHDL.
In Vivado versions prior to 2014.1, both instances are present in the synthesized design.
Starting from 2014.1, one FIFO instance is present, but the other macro instance is being trimmed by Synthesis.
COMPONENT FIFO_SYNC_MACRO
generic (
......
u_fifo0 : FIFO_SYNC_MACRO
generic map (
......
u_fifo1 : FIFO_SYNC_MACRO
generic map (
......
How can I resolve this issue?
解决方案
The correct usage for unimacros with VHDL is to put the library unimacro and use clause inside the HDL as in the below example:
library unimacro;
use unimacro.vcomponents.all;