AR# 59599
|Vivado Simulator FAQ - How do I speed up simulation?
描述
What options are available in Vivado to reduce the simulation runtime with the minimum impact on the functionality of my 7 Series design?
解决方案
The UNIFAST library is an optional library that can be used during RTL behavioral simulation to speed up simulation runtime of 7 Series designs.
Xilinx recommends using the UNIFAST library for initial verification of the design and when running a complete verification use the UNISIM library.
The simulation runtime speed-up is achieved by supporting a subset of the 7 Series primitive features in the simulation mode.
The 7 Series primitives listed below have an equivalent UNIFAST model:
- MMCME2
- RAMB18E1/RAMB36E1
- FIFO18E1/FIFO36E1
- DSP48E1
- GTHE2_CHANNEL/GTHE2_COMMON
- GTXE2_CHANNEL/GTXE2_COMMON
The UNIFAST model is provided in both VHDL & Verilog versions and is located in the following directories:
- Verilog: <Vivado_Install_Dir>/data/verilog/src/unifast
- VHDL: <Vivado_Install_Dir>/data/vhdl/src/unifast
Recommended method for simulation with all UNIFAST models:
To enable UNIFAST support in a Vivado project environment for the Vivado simulator or ModelSim, check the Enable fast simulation models box, as shown below:
unifast.PNG
For IES and VCS simulators, point to the UNIFAST library using:
-y ../verilog/src/unifast
IMPORTANT NOTE:
- This model cannot be used for timing-driven simulations.
- UNIFAST libraries cannot be used for sign-off simulations because the library components do not have all of the checks/features that are available in a full model.
- UltraScale primitive models are already optimized for runtime and are thus not supported