AR# 58738

描述

Version Found:

v3.0 (7 Series Integrated Block for PCI Express)
v2.3 (AXI Bridge for PCI Express)

Version Resolved and other Known Issues: 

See (Xilinx Answer 54643) for 7 Series Integrated Block for PCI Express
See (Xilinx Answer 54646) for AXI Bridge for PCI Express

7 Series "Integrated Block for PCI Express" and "AXI Bridge for PCI Express" Cores are not available in the IP catalog for Zynq 7015 (clg485 package) / Artix 35t (cpg236 and csg325 packages) and 50t devices.

解决方案

This is a known issue in Vivado 2013.4 to be fixed in a future release of the core. 

Please install the patch attached with this answer record to enable generation of the core in Artix 35t (cpg236 and csg325 packages), Artix 50t and 2013.4 for Zynq 7015 (clg485 package) devices. 

Gen2x4 core for the -1 Speedgrade in Zynq 7015 (clg485 package) is not supported in this release.

Two separate patches have been provided for 7 Series "Integrated Block for PCI Express" and "AXI Bridge for PCI Express" Cores.

Follow the instructions below to install the patches:

Extract the contents of the patches  to the desired patch directory location.

Set the MYVIVADO environment variable to point to the 'vivado' directory inside the patches directory.

Linux:

setenv MYVIVADO <..>/ar_58738_pcie_7x_0_v3_0_Rev_1_preliminary_patchrev1/vivado

Windows:

SET MYVIVADO=<..>/ar_58738_pcie_7x_0_v3_0_Rev_1_preliminary_patchrev1/vivado

Run Vivado from the original location.

If the patch has been successfully applied, the Vivado version displayed in the output will be updated.

Note: For successful bitstream generation, a patch provided in (Xilinx Answer 58986) must also be installed.

Revision History
02/28/2014 - Initial release

03/07/2014 - Updated for Artix 35t and 50t devices

附件