AR# 58667

描述

Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 54025)

When upgrading a MIG 7Series design that has sys_clk set with "No Buffer" and running Out of Context (OOC) flow, synthesis fails with errors similar to the following:

Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 817.828 ; gain = 198.367
---------------------------------------------------------------------------------
ERROR: [Synth 8-439] module 'ddr3' not found
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 852.641 ; gain = 233.180
---------------------------------------------------------------------------------
RTL Elaboration failed
    while executing
"rt::run_rtlelab -module $rt::top"
    invoked from within
"if {$rt::useElabCache == false} {
      rt::run_rtlelab -module $rt::top
    }"
    ("uplevel" body line 87)
    invoked from within
"uplevel #0 {
    set ::env(BUILTIN_SYNTH) true
    source $::env(HRT_TCL_PATH)/rtSynthPrep.tcl
    set rt::cmdEcho 0
    rt::set_parameter writeXmsg t..."
ERROR: [Common 17-39] 'source' failed due to earlier errors.
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
ERROR: [Common 17-39] 'source' failed due to earlier errors.

    while executing
"source -notrace ./.Xil/Vivado-13731-xsjaria/realtime/ddr3.tcl"
    invoked from within
"synth_design -top ddr3 -part xc7k325tffg900-1 -mode out_of_context"
    (file "ddr3.tcl" line 26)
INFO: [Common 17-206] Exiting Vivado at Wed Nov 27 17:44:57 2013...

解决方案

To work around this issue, sys_clk needs to be Differential or you have to explicitly specify the sys_clk.

Revision History
12/18/2013 - Initial release

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