AR# 5864

描述

General Description:

If you are using SRL16 and SRL16_1 components, using RISING and

FALLING tags to make more refined groups, will put both types in both

groups.

For Example in the UCF File:

TIMEGRP RISING_CLK=Rising;

TIMEGRP FALLING_CLK=Falling;

Produces the Following in the PCF File:

TimeGroup RISING_CLK:

BELs:

CntA/count[0] CntA/count[1] CntA/count[2] CntA/count[3]

CntA/count[4] CntA/count[5] CntC/count[2] CntC/count[3]

CntC/count[4] CntC/count[5] CntC/count[0] CntC/count[1]

in_a2 in_a1 out_a in_b1

DlyB/SRL16E DlyA/SRL16E

TimeGroup FALLING_CLK:

BELs:

out_b in_b2 DlyB/SRL16E DlyA/SRL16E

Both the DlyA and DlyB SRL16 components are being placed in both the

RISING_CLK and FALLING_CLK timing groups. But the DlyA is a Falling

Edge Clock and the DlyB is a Rising Edge Clock, so the TimeGroups are incorrect.

解决方案

As a workaround you can use the EXCEPT syntax to create a new

RISING and FALLING group and new groups for the DlyA and DlyB

as follows:

INST "DlyB/SRL16E_Instance_Name" TNM=SRL16_1_GROUP;

INST "DlyA/SRL16E_Instance_Name" TNM=SRL16_GROUP;

TIMEGRP REALLY_RISING = RISING : EXCEPT : SRL16_1_GROUP ;

TIMEGRP REALLY_FALLING = FALLING : EXCEPT : SRL16_GROUP ;

Where SRL16_1_GROUP is a group of falling edge SRL16s and

SRL16_GROUP is a group of rising edge SRL16s.