AR# 58628

描述

Version Found: v3.0
Version Resolved and other Known Issues: See (Xilinx Answer 54643)

The design does not meet timing requirements when implementing the example design on Artix xc7a200t devices with the following configuration:

Language: VHDL
Device Port/Type: Root Port
Maximum Link Speed: Gen2
Number of Lanes: x4
AXI Interface Width: 64-bit
Max Payload Size: 128 Bytes

The tool issues the following warning message:

CRITICAL WARNING/proj [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.

解决方案

This is a known issue to be fixed in a future release of the core.

It is recommended that you work around this issue by selecting 128-bit for the 'AXI Interface Width' instead of 64-bit.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
12/18/2013 - Initial release

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