If a ROM in the HDL code has a sequence such as input register + ROM + output register, and the input register is incompatible such as Asynchronous, Vivado Synthesis does not allow ROM to be packed into the block RAM.
How do I fix this issue? Is there a work-around?
The work-around is to apply "Keep" in the interface between input register and the ROM and this will allow Vivado Synthesis to pack the ROM into the block RAM.
| AR# 57981 | |
|---|---|
| 日期 | 10/22/2013 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| Tools | |