AR# 57716

描述

In the Verilog "Language Template" of the PlanAhead tool for Mealy binary state machines, the attribute "FSM_ENCODING" is incorrect. The word "Sequential" is incorrectly spelled.

The current content:

(* FSM_ENCODING="SEQUNTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [3:0] state = <state1>;

It should be:

(* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [3:0] state = <state1>;

解决方案

The issue has been fixed in the Vivado Language Templates.