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  4. AR# 57538: Aurora 8B10B - Virtex-6 - CDR settings for synchronous operation

AR# 57538

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Aurora 8B10B - Virtex-6 - CDR settings for synchronous operation

描述

For Virtex-6 GTX, the Aurora 8B10B core enables the second order loop for the CDR (PMA_RX_CFG) to support asynchronous clocking setup between the link partners.

In a synchronous clocking setup, the default CDR settings for the Aurora core can result in unstable reset behavior of the core, especially when a cable plug-out --> plug-in operation is performed.

This answer record provides the required settings for enabling first or second order loop in CDR.

解决方案

The default CDR settings for Aurora are set to support a +/- 200ppm difference between channel partners.

If the channel partners are synchronous or have a difference < +/-200ppm in the design, a different value for the CDR setting (PMA_RX_CFG) needs to be used to enable only the first order loop.

Below are the settings for PMA_RX_CFG:

Synchronous clocking: 0x05CE008 - first order loop enabled.

Asynchronous clocking: 0x05CE049 - second order loop enabled.

Revision history:

5/30/2014 - Initial Release

AR# 57538
日期 01/08/2015
状态 Active
Type 综合文章
器件
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