解决方案
Overview:
IUS (NCSim) provides two methods of referencing Xilinx model libraries for Functional and Gate Level Simulation: Precompiled and Dynamic.
Notes:
The method of library reference in Vivado has changed from ISE.
The changes of note are:
- The UNISIM library now contains both functional and timing simulation models.
- A parameter xil_timing now indicates whether UNISIM models are functional or timing.
- A retarget library has been included for legacy device functional and timing simulation component models.
- XilinxCoreLib is not required for Vivado simulation. It can be included if an ISE based legacy IP is present.
- The AXI BFM is license based, and requires a separate compilation step if licensed and used in the design.
- The Vivado physical library directory path has changed from the ISE location (Logical Libraries are the same)
For more information, see Vivado Design Suite User Guide Logic Simulation (
UG900).
Dynamic Library Compilation for Verilog Functional Simulation
Functional Simulation Command using IUS (NCSim)
irun -loadvpi $XILINX_VIVADO/ids_lite/ISE/lib/lin64/libxil_ncsim.so:xilinx_register_systf.xilinx_register_systf +access+rw -64bit
-f $XILINX_VIVADO/data/secureip/secureip_cell.list.f \
-f $XILINX_VIVADO/data/secureip/axi_bfm/axi_bfm_cell.list.f \
-y $XILINX_VIVADO/data/verilog/src/unisims +libext+.v \
-y $XILINX_VIVADO/data/verilog/src/unimacro +libext+.v \
-y $XILINX_VIVADO/data/verilog/src/retarget +libext+.v \
-f customer_file_list.f $XILINX_VIVADO/data/verilog/src/glbl.v
-loadvpi <file> : load the licensing library for simulation (AXI BFM)
-y : include subdirectories
-f : include file list
Library Notes:
unisims : Xilinx primitive functional models
unimacro : Macros models for large scale primitives
retarget : unisim/simprim retarget library for older architectures
XilinxCoreLib : ISE legacy IP models
secureip_cell.list : List of secure IP components for inclusion
axi_bfm_cell.list : Optional Encrypted AXI BFM model (requires license)
customer_file_list.f : A customer file list constraining the file names to be simulated
Dynamic Library Compilation for Verilog Timing Simulation
Timing simulation is a three step process consisting of:
- Generating the simulation netlist (timesim.v generation)
- Annotating timing information to the netlist (SDF file generation)
- Analyzing, elaborating, and simulating the timing netlist and SDF using IUS (NCSim)
Timing Netlist/SDF Generation in Vivado:
write_verilog -mode timesim -sdf_file <sdf_file>.sdf <sim_netlist>.v
write_sdf <sdf_file>.sdf
Timing Simulation Command in IUS (NCSim)
irun -sdf_file <sdf_file>.sdf -y $XILINX_VIVADO/data/verilog/src/unisims \
$XILINX_VIVADO/data/verilog/glbl.v \
-f $XILINX_VIVADO/data/secureip/secureip_cell.list.f \
<testfixture>.v <sim_netlist>.v
IUS (NCSim) Option Notes:
-y : include library subdirectories
-f : include file list
unisims : Xilinx primitive functional/timing models