AR# 56231

描述

Version Found: MIG 7 Series v1.6
Version Resolved: See (Xilinx Answer 54025)

In some configurations, MIG 7 Series assigns an Address/Ctrl group to a byte lane with no signals in it. 

For example, MIG 7 Series may assign Address/Ctrl 0-2 and DQ[0-7] in one bank, and then DQ[8-15] in another where Address/Ctrl0 has no signals. 

In this case, an interface that should fit into one bank gets split into two.  

MIG should never assign a byte group with no signals.  

This will be resolved in a future release.  Please see the following manual work around.

解决方案

This can be manually worked around by unassigning the empty byte group. 

In the example above, Address/Ctrl-0 can be unassigned and then the second data byte can be moved into that bank to contain the interface in a single bank. 

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