AR# 56217

描述

Version Found: v1.8.a
Version Resolved: See (Xilinx Answer 54025)

The MIG 7 Series RLDRAM 3 v1.8.a design also uses a bus turnaround time of 8 CK/CK# cycles to account for input timing skew and data bus contention.

解决方案

This latency can be reduced from 8 down to 4 to improve the turnaround latency and improve bus efficiency.

To change the bus turnaround latency, the following code changes must be done in mig_7series_v1_8_rld_mc.v:

Change

localparam WR_TO_RD_CHK = (MEM_TYPE=="RLD2_CIO" || MEM_TYPE == "RLD3") ? 8 : 0;
localparam RD_TO_WR_CHK = (MEM_TYPE=="RLD2_CIO" || MEM_TYPE == "RLD3") ? 8 : 0; //12

To

localparam WR_TO_RD_CHK = (MEM_TYPE=="RLD2_CIO" || MEM_TYPE == "RLD3") ? 4 : 0;
localparam RD_TO_WR_CHK = (MEM_TYPE=="RLD2_CIO" || MEM_TYPE == "RLD3") ? 4 : 0; //12

Note: The latency must be in multiples of 4 CK cycles as a result of the 1/4 rate memory controller.

Revision History
06/19/2013 - Initial release

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