AR# 56101

描述

The XDC file produced on generation of a System Generator design will include a "create_clocks" constraint. 

However, this System Generator project is included in larger overall systems in Vivado which will already have clocks defined or created. 

This can lead to incorrect constraints being applied and possible system issues in a design as in the examples below:

• The user writes the constraint below in their own xdc file.
  

  create_clock -name clk -period 200 [get_ports clk]

  This constraint would overwrite the Sysgen constraint resulting in the Sysgen module becoming unconstrained.
   
• The Sysgen module is instantiated as a submodule.
  The clocks coming from an MMCM are generated, and the constraints are propagated with jitter, phase shifting, etc.
  Another primary clock is added to the Sysgen module.
  This primary clock is now starting at 0, with no jitter, no phase shifting, etc. which will lead to incorrect timing analysis.

Is it possible to avoid these potential issues?

解决方案

To work around these issues, ignore the System Generator XDC file, or modify it to remove the "create_clock" constraint in the Vivado project.

From release 2013.2 on, if the Vivado Sysgen output products are created from within the Vivado project, then the "create_clock" constraint is not included in the XDC file and no conflict occurs.