AR# 5572

描述

解决方案

Use the following constraint on the signal that you wish to place on a global net: 

BUFG=CLK|OE|SR; 

WARNING: For the XC9500/XL/XV and CoolRunner-II families, this constraint makes the global pin active. 

Be sure that a global pin used in this way is unconnected on the board. 

For example: 

To place an internally generated node on a global clock buffer, enter the following in your UCF: 

net my_net BUFG=CLK; 

Replace "CLK" with "OE" for a global output enable or "SR" for a global set/reset. 

This solution does not apply to the CoolRunner XPLA3 device because the global clock pins do not support bi-directional logic. 

Additionally, XPLA3 devices do not have global set/reset/output enable pins. 

For other common CPLD questions, refer to the CPLD FAQ: (Xilinx Answer 24167)

附件