AR# 5540: 1.5i Virtex PAR - Placer seg faults when both list and single LOC csts applied to a TBUF set.
AR# 5540
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1.5i Virtex PAR - Placer seg faults when both list and single LOC csts applied to a TBUF set.
描述
Design contains nets that are driven by two TBUFs. On each of these TBUF nets, one of the TBUFs is LOC'ed to a single location on the right-side of the chip. List constraints are applied to the second TBUF and these constraints direct it towards the left-side of the chip. Placer core dumps during the random drop initial placement.