AR# 55311

描述

Version Found: v1.9/v2.0

Version Resolved and other Known Issues:

• See (Xilinx Answer 40469) for v1.9
• See (Xilinx Answer 54643) for v2.0

When simulating a 7 Series Integrated Block for PCI Express v1.9/v2.0 VHDL example design generated for 128-bit interface width, downstream Memory Write transactions fail.

解决方案

This is a known issue and is scheduled to be fixed in a future release of the core.

To work around this issue, make the following modification in PROC_TX_MEMORY_WRITE_64 in "test_interface.vhd":

 case ((int_length -1) mod 4) is
        --when 1 => trn_trem_n_c <= "11";
        --when 2 => trn_trem_n_c <= "10";
        --when 3 => trn_trem_n_c <= "01";
        --when 0 => trn_trem_n_c <= "00";
          when 0 => trn_trem_n_c <= "11";
          when 1 => trn_trem_n_c <= "10";
          when 2 => trn_trem_n_c <= "01";
          when 3 => trn_trem_n_c <= "00";
          when others => null;
      end case;

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

04/03/2013 - Initial release