This answer record provides information on some Vivado Synthesis switch options (RTL, GUI, TCL) equivalent to XST.
The answer record provides a tabular column comparing XST and Vivado Synthesis switch options, which can be used as a reference when a user transitions from XST to Vivado Synthesis and is in need of a quick reference guide.
This answer record will serve that purpose.
Note: This Answer Record is a part of the Xilinx Solution Center for Vivado Synthesis (Xilinx Answer 55265), which is available to address all questions related to Vivado Synthesis.
Whether you are starting a new design or troubleshooting a problem, use the Solution Center for Vivado Synthesis to guide you to the right information.
Below is a table of equivalent switches:
| Name | XST Equivalent | Vivado Equivalent | Available for |
|---|---|---|---|
| keep_hierarchy | keep_hierarchy (RTL/GUI) | keep_hierarchy (RTL), -flatten_hierarchy (GUI/TCL) | VHDL, Verilog |
| black box | BoxType (RTL) | black_box (RTL) | VHDL, Verilog |
| buffer type | buffer_type (RTL) | NA | VHDL, Verilog |
| full case | vldcase (GUI), full_case (RTL) | full_case (RTL) | Verilog |
| gated clock | N/A | gated_clock_conversion, gated_clk (RTL/GUI/TCL) | VHDL, Verilog |
| Keep | Keep (RTL) | keep (RTL) | VHDL, Verilog |
| Max fanout | max_fanout (RTL/GUI) | fanout_limit (TCL/GUI), MAX_FANOUT (RTL) | VHDL, Verilog |
| Parallel Case | vldcase (GUI), parallel_case (RTL) | parallel_case (RTL) | Verilog |
| RAM Style | ram_style (RTL/GUI) | ram_style (RTL), ram_style (TCL - Hidden) | VHDL, Verilog |
| ROM Style | rom_style (RTL/GUI) | rom_style (RTL) | VHDL, Verilog |
| Translate off, Translate on | synthesis translate_off, synthesis translate_on (RTL) | synthesis translate_off, synthesis translate_on (RTL) | VHDL, Verilog |
| use dsp48 | use_dsp48 (RTL/GUI) | use_dsp48 (RTL) | VHDL, Verilog |
| add IO buffers | iobuf (GUI) | no_iobuf (GUI/Tcl - Hidden), -mode out_of_context (Tcl/GUI - Recommended) | VHDL, Verilog |
| FSM Extraction/ FSM Style | fsm_extract (RTL/GUI) | fsm_extraction (GUI/TCL) | VHDL, Verilog |
| Equivalent Register Removal | equivalent_register_removal (RTL/GUI) | keep_equivalent_registers (GUI/TCL) | VHDL, Verilog |
| Resource Sharing | resource_sharing (RTL/GUI) | resource_sharing (TCL/GUI) | VHDL, Verilog |
| Generate RTL Schematic | rtlview (GUI) | -rtl (TCL) | VHDL, Verilog |
| BUFG | bufg (GUI) | bufg (TCL/GUI) | VHDL, Verilog |
| Netlist Hierarchy | netlist_hierarchy (GUI) | N/A | VHDL, Verilog |
| Verilog Include Directories | vlgincdir (GUI) | include_dirs (TCL), Verilog options - verilog_dir (GUI) | Verilog |
| Generics | generics (RTL/GUI) | generic (RTL/TCL) | VHDL, Verilog |
| Verilog Macros | define (GUI) | verilog_define (TCL) | Verilog |
| Optimization Effort | opt_level (RTL/GUI) | effort_level (TCL - Hidden) | VHDL, Verilog |
| BRAM Utilization | bram_utilization_ratio (GUI) | max_bram (TCL - Hidden) | VHDL, Verilog |
| DSP Utilization | dsp_utilization_ratio (GUI) | max_dsp (TCL - Hidden) | VHDL, Verilog |
| Safe Implementation | safe_implementation (RTL/GUI) | fsm_safe_state (RTL/TCL) | VHDL, Verilog |
| Shift Register Extraction | shreg_extract (RTL/GUI) | shreg_extract (RTL/TCL) | VHDL, Verilog |
| Shift Register Minimum Size | shreg_min_size (GUI) | shreg_min_size (GUI/TCL) | VHDL, Verilog |
| LUT Combining | lc (GUI) | no_lc (GUI/TCL) | VHDL, Verilog |
| Reduce Control Sets | reduce_control_sets (GUI) | control_set_opt_threshold (GUI/TCL) | VHDL, Verilog |
| Directive | N/A | directive (GUI/TCL) | VHDL, Verilog |
| Don't Touch | N/A | dont_touch (RTL/TCL) | VHDL, Verilog |
| FSM Encoding | fsm_encoding (RTL/GUI) | fsm_encoding (RTL) | VHDL, Verilog |
| SRL Style | N/A | srl_style (RTL) | VHDL, Verilog |
| ASYNC_REG | N/A | ASYNC_REG (RTL) | VHDL, Verilog |
| Buffer Insertion | N/A | io_buffer_type (RTL) | VHDL, Verilog |
| Clock buffer insertion | N/A | clock_buffer_type (RTL) | VHDL, Verilog |
| Direct Enable | N/A | DIRECT_ENABLE (RTL) | VHDL, Verilog |
| Direct Reset | N/A | DIRECT_RESET (RTL) | VHDL, Verilog |
| Cascade DSP | N/A | cascade_dsp(GUI) | VHDL, Verilog |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 55264 | Xilinx Solution Center for Vivado Synthesis - Design Assistant | N/A | N/A |
| AR# 55185 | |
|---|---|
| 日期 | 01/20/2016 |
| 状态 | Active |
| Type | 解决方案中心 |
| Tools | |