2. 技术支持
  3. AR# 55056: MIG 7 Series DDR2/DDR3 - AXI Interface Enabled - During continuous read or write commands, bubbles/gaps are seen between the user interface bursts

AR# 55056

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MIG 7 Series DDR2/DDR3 - AXI Interface Enabled - During continuous read or write commands, bubbles/gaps are seen between the user interface bursts

描述

Version Found: MIG 7 Series v1.8
Version Resolved: See (Xilinx Answer 45195)

When the MIG 7 Series DDR3/DDR2 controller with the AXI interface enabled receives continuous read or write commands, there will be bubbles/gaps between the user interface app signals. 

This results in a loss of efficiency.

解决方案

This behavior is caused by the AXI write and read state machine.

The state machine cannot continuously send out UI commands.

When the AXI burst is short, it will result in the greatest performance loss.

The current workaround is to use long AXI bursts, which will reduce the bubbles/gaps but will not remove them completely.

This issue is fixed in the 2013.2 release.
AR# 55056
日期 08/13/2014
状态 Active
Type 综合文章
器件
IP
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