AR# 54795

描述

I have an Implemented design.

After running the DRC check or when attempting to generate the Bitstream, I receive the following ERROR message:

ERROR: [Drc 23-20] Rule violation (RTSTAT-5) Partial antenna - <xxx> net(s) have a partial antenna. The problem net ...

How can this be fixed?

解决方案

The partial antenna message should not happen in any design. 

This means there are some nets with endpoints not connected to any PIN, which could cause problems when the design is loaded into the FPGA.

To work around this problem you can try to reroute the nets involved from the Vivado GUI or the Tcl command window.

For the Tcl command window you need to follow the steps bellow:

1. Select the error message and find out the name of the nets failing.
    
2. Unroute  those nets with the command:
   

   route_design -unroute -nets [get_nets <net_name>]

3. Reroute the nets with the command:
   

   route_design -nets [get_nets <net_name>] -effort_level high

4. Check that the previous nets were routed with the DRC check tool:
   

   report_drc -name <report_name> -rules RTSTAT-5 -verbose

   
   (The partial antenna rule is defined under the DRC rule RTSTAT-5)

For Vivado GUI steps, please refer to (Xilinx Answer 54683)

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