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  3. AR# 5249: SYNPLIFY: How to preserve a signal through synthesis using the syn_keep attribute?

AR# 5249

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SYNPLIFY: How to preserve a signal through synthesis using the syn_keep attribute?

描述


General Description: How to preserve a signal or wire through Synplify,

so it does not get optimized?



The syn_keep attribute is declared on a wire or signal. This attribute

preserves the specified wire through synthesis and prevents it from

being optimized out in the final design.



NOTE: Use Synplify 5.0.8 or greater.

解决方案


VHDL

-----



library synplify;

use synplify.attributes.all;



entity example is

port ( <port list> )

end entity;



architecture XILINX of example is



signal temp : bit_vector (7 downto 0);

attribute syn_keep of temp : signal is true;



Verilog

-----



module example (<port list>);



wire [7:0] temp /* synthesis syn_keep = 1 */;
AR# 5249
日期 05/16/2011
状态 Archive
Type 综合文章
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