These are correct warnings.
These warnings indicate that there are circular dependency issue in the design.
The following is an example of the circular dependency situation.
Supposing a.vhd is compiled to library a_lib. And a.vhd has the following use clause.
library b_lib;
use b_lib.all;
Then b.vhd is compiled to library b_lib. And b.vhd has the following use clause.
library a_lib;
use a_lib.all;
This makes a.vhd and b.vhd dependent on each other. And this is a circular dependency.
To resolve these warnings, do not write use clause to specify entire content of the library (like use <lib_name>.all).
Instead, use specific packages (use <lib_name>.<package_name>). Also, remove the unnecessary library definitions.
Here are few more possible workaround to this problem:
1. Merge the VHDL entity and architecture into one VHDL file.
2. a) Select the No Update, Manual Compile Order in the Hierarchy Update Tab either in the Hierarchy field or Compile Order field.
b) Move the Architecture file before the Entity file for those files Vivado Synthesis generated the [Synth 8-1940] error message.
c) Run Vivado Synthesis; this should allow synthesis to run successfully.
3. If there is only a warning and the design finishes without an Error message, the user should be able to move on to the next step.