2. 技术支持
  3. AR# 5128: LogiCORE PCI - When is the S_WRDN signal valid?
  4. AR# 51285: 7 Series Integrated Block Wrapper for PCI Express v1.6 (Vivado 2012.2) - Does not link train with XCV72000T devices

AR# 51285

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7 Series Integrated Block Wrapper for PCI Express v1.6 (Vivado 2012.2) - Does not link train with XCV72000T devices

描述

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

If implementing the 7 series Integrated Block Wrapper for PCI Express v1.6 core on XC7V2000T devices, the link does not come up.

解决方案

The default value for PCIE_USE_MODE parameter in the generated core wrapper is "3.0."
To resolve the link training issue, change this parameter value to "1.0."

Revision History
08/15/2012 - Initial release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 51285
日期 02/15/2013
状态 Active
Type 已知问题
器件
Tools
IP
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