解决方案
The following table shows all the Zynq device/package combinations with transceivers:
1. XC7Z030 device - FBG484, FBG676, FFG676 packages
2. XC7Z045 device - FBG676, FFG676, FFG900 packages
| Package |
FBG484 |
FBG676 |
FFG676 |
FFG900 |
| Zynq |
No of GTX |
Max line rate |
No of GTX |
Max line rate |
No of GTX |
Max line rate |
No of GTX |
Max line rate |
| XC7Z030 |
4 |
6.6 Gb/s |
4 |
6.6 Gb/s |
4 |
12.5 Gb/s |
|
|
| XC7Z045 |
|
|
8 |
6.6 Gb/s |
8 |
12.5 Gb/s |
16 |
12.5 Gb/s |
For GTX transceiver support on these Zynq devices, please follow the following steps to be able to generate core files by invoking similar Kintex-7 devices from the Coregen:
For Zynq XC7Z030 device - All packages:
1. Select a Kintex-7 device with 4 GTX transceivers from CORE Generator (for example,XC7K160T FBG484).
2. Limit the maximum line rate to 6.6 Gb/s if you need the core files for an FBG package, even if the GUI allows for a higher line rate (For Kintex-7 devices the maximum line rate is not dependent on package type and can be up to 12.5 Gb/s for all packages while in Zynq it is limited to 6.6 Gb/s for FBG packages and is 12.5 Gb/s for FFG packages).
3. Open the UCF/XDC file and change the constraints and pin locations based on the inputs from FPGA editor.
For Zynq XC7Z045 device FBG676 & FFG676 packages:
1.Select a Kintex-7 device with 8 GTX transceivers from CORE Generator (for example,XC7K325T FBG676).
2. Limit the maximum line rate to 6.6 Gb/s if you need the core files for an FBG package even if the GUI allows for a higher line rate ( For Kintex-7 devices the maximum line rate is not dependent on package type and can be up to 12.5 Gb/s for all packages while in Zynq it is limited to 6.6 Gb/s for FBG packages and is 12.5 Gb/s for FFG packages).
3. Open the UCF/XDC file and change the constraints and pin locations based on the inputs from FPGA editor.
For Zynq XC7Z045 device FFG900 package:
1. Select a Kintex-7 device with 16 GTX transceivers from CORE Generator(for example,XC7K325T FFG900).
2. Open the UCF/XDC file and change the constraints and pin locations based on the inputs from FPGA editor.
Note: If the implementation scripts generated with the example design are used, then replace the Kintex-7 device selected above with the correct Zynq device and package in the "implement.sh", "implement.bat", "planahead_rdn.tcl", "xst.scr" files.