AR# 47634

描述

解决方案

The list of blocks removed from System Generator for Vivado design tools is as follows:

CIC Compiler 1.1
CIC Compiler 1.2
CIC Compiler 1.3
CIC Compiler 2.0
CORDIC 4.0
ChipScope'
Complex Multiplier 3.0
Complex Multiplier 3.1
Complex Multiplier 4.0
Convolution Encoder 7.0
Convolutional Encoder v3_0
Convolutional Encoder v6_0
DDS Compiler 2.1
DDS Compiler 3.0
DDS Compiler 4.0
xbsIndex_r4/DAFIR v9_0
DDS Compiler v1_1
DDS v4_0
DDS v5_0
DSP48 Macro'
DSP48 Macro/Xo'
DSP48 Macro/Yo'
DSP48 Macro/No'
DSP48 Macro/DSP48'
DSP48 Macro/xlmacroissueengine'
DSP48 Macro/xlreinterpretdsp48macro'
DSP48 Macro/P'
Divider Generator 2.0
Divider Generator 3.0
EDK Processor'
EDK Processor/Copyright'
FFT v1_0
FFT v3_1
FFT v3_2
FFT v4_1
FFT v5_0
FIR Compiler 4.0
FIR Compiler 5.0
FIR Compiler 6.0
FIR Compiler 6.1
FIR Compiler 6.2
FIR Compiler v1_0
FIR Compiler v2_0
FIR Compiler v3_0
FIR Compiler v3_1
FIR Compiler v3_2
Fast Fourier Transform 6.0
Fast Fourier Transform 7.0
Fast Fourier Transform 7.1
From FIFO'
From Register'
Interleaver Deinterleaver 5.1
Interleaver Deinterleaver v4_0
Interleaver Deinterleaver v5_0
Interleaver//De-interleaver 6.0
Multiple SubsystemGenerator'
PicoBlazeMicrocontroller'
PicoBlaze InstructionDisplay'
PicoBlaze InstructionDisplay/Instruction'
PicoBlaze InstructionDisplay/Program Counter'
PicoBlaze InstructionDisplay/BusCreator'
PicoBlaze InstructionDisplay/Clock Probe'
PicoBlaze InstructionDisplay/Constant'
PicoBlaze InstructionDisplay/Constant0'
PicoBlaze InstructionDisplay/Instruction Gate'
PicoBlaze InstructionDisplay/MultiportSwitch'
PicoBlaze InstructionDisplay/PC Gate'
PicoBlaze InstructionDisplay/Write Display'
PicoBlaze InstructionDisplay/Write Display/In1'
PicoBlaze InstructionDisplay/Write Display/Trigger'
PicoBlaze InstructionDisplay/Write Display/S-Function'
RS Decoder v5_1
RS Decoder v6_0
RS Encoder v5_0
RS Encoder v6_0
Reed-Solomon Decoder 6.1
Reed-Solomon Decoder 7.0
Reed-Solomon Decoder 7.1
Reed-Solomon Encoder 6.1
Reed-Solomon Encoder 7.0
Reed-Solomon Encoder 7.1
Resource Estimator'
Shared Memory'
Shared Memory Read'
Shared Memory Write'
SineCosine'
To FIFO'
To Register'
VDMA Interface 4.0
VDMA Interface 5.0
Viterbi Decoder 7.0
Viterbi Decoder v5_0
Viterbi Decoder v6_0
Viterbi Decoder v6_1
WaveScope

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

链接问答记录

主要问答记录