Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 40469)
There are certain IP configurations that do not meet timing.
This is a known issue and will be fixed in a future release of the core. If you run intotiming violations with theimplementation of the default core generation, please create aWebCase with Xilinx Technical Supportand submit the XCO file and the timing report.
NOTE: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Revision History
05/08/2012 - Initial release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 40469 | 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
| AR# 47628 | |
|---|---|
| 日期 | 05/20/2012 |
| 状态 | Active |
| Type | 已知问题 |