2. 技术支持
  3. AR# 4673: SYNPLIFY: How to change the initialization state of a flip-flop using INIT?

AR# 4673

|

SYNPLIFY: How to change the initialization state of a flip-flop using INIT?

描述

Keywords: INIT, Synplify, Verilog, VHDL

Urgency: Standard

General Description:
How to change the initialization state of a FF?

For XC4000 devices, when a preset or clear pin on a flip-flop is
connected to an active signal, the state of that signal controls the
startup state of the flip-flop. For example, if you connect an active
signal to the preset pin, the flip-flop starts up in the preset state.
If you do not connect the clear or preset pin, the default startup
state is a clear state. To change the default to preset, assign an
INIT=S attribute to the flip-flop.

By default, all registers in an XC9500 device are initialized to
zero when powered up. The registers in XC9000 macrocells have both
asynchronous clear and asynchronous preset controls available. So,
the initial power-on states of CPLD macrocell registers can be
selected regardless of whether the register is asynchronously cleared
(INIT=R) or preset (INIT=S) during operation.

解决方案

1

Verilog
-------

module d_register (CLK, D_IN, Q_OUT);
input CLK;
input [3:0] D_IN;
output [3:0] Q_OUT;

reg [3:0] Q_OUT /* synthesis xc_props="INIT=R" */ ;

always @ (posedge CLK)
Q_OUT <= D_IN;

endmodule

2

VHDL
----

library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;

entity d_register is
port (CLK : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR(3 downto 0);
Q_OUT : out STD_LOGIC_VECTOR(3 downto 0));
attribute xc_props of Q_OUT : signal is "INIT=R";
end d_register;

architecture XILINX of d_register is

begin

process (CLK)
begin
if rising_edge(CLK) then
Q_OUT <= D_IN;
end if;
end process;

end XILINX;

3

SDC
---

define_attribute {Q[3:0]} xc_props {INIT=R}
AR# 4673
日期 04/24/2007
状态 Archive
Type 综合文章
People Also Viewed