AR# 45696

描述

This answer record highlights the important requirements and known issues for the Kintex-7 FPGA General Engineering Sample (ES) program related to software and IP. These items are specifically relevant to designs targeting the Kintex-7 325T and 410T General ES devices(marked as CES). Additional silicon limitations might exist, so please reference the 7 Series FPGA errata online. The errata document also outlines specific part markings and JTAG Revision IDs.

This answer record will be updated as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.

解决方案

Software Requirements

• ISE Design Suite 13.4, available on the Xilinx Download Center, is required for use ofGeneral ES silicon forKintex-7 devices
• Patches - this is the complete list of available patches for ISE 13.4 design tools targeting the Kintex-7 General ES silicon
  
  • Required patches for all users:
    • None
  • Required patches based on usage:
    • (Xilinx Answer 45653) - Required patch if using MIG DDR2/DDR3 memory interface
    • (Xilinx Answer 45870) - ISE 13.4 BitGen, 7 Series - Unexpectedly long delay through input when using low voltage standard

Software Known Issues

• (Xilinx Answer 40905) - 13.x Software Known Issues Related to the 7 Series FPGAs

IP Requirements

All 7 Series IP Cores are listed as Pre-production in the CORE Generator "Status" field. Support of Pre-production cores on General ES FPGA devices is dependent on Xilinx hardware validation, which will be ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues Answer Records (below) for the most recent information. The list below includes all Pre-Production IP cores that have been hardware validated on General ES at this time:

• 7 Series Integrated Block for PCI Express
• MIG 7 Series DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II
• XAUI
• Ethernet 1000BASE-X PCS/PMA or SGMII
• Tri-Mode Ethernet MAC

This list will be updated as hardware validation is completed. If there are further questions about hardware validation for a particular IP core, please contact a Field Application Engineer.

IP Known Issues

• 7 Series Integrated Block for PCI Express
  • All General ES silicon users targeting the Integrated Block for PCI Express must update to 13.4 and use the v1.3 release. During core customization select GES when asked for silicon revision type.
  • (Xilinx Answer 40469) 7 Series Integrated Block Wrapper for PCI Express - Release Notes and Known Issues
• MIG 7 Series DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II
  • (Xilinx Answer 45653)MIG 7 Series v1.4 DDR2/DDR3 - Calibration fails at OCLK_DELAY Calibration Stage
• XAUI
  • All General ES silicon users must update to ISE 13.4 software and use the XAUI v10.2 release
  • (Xilinx Answer 45705) LogiCORE IP XAUI v10.2 - Release Notes and Known Issues for ISE Design Suite 13.4
• Ethernet 1000BASE-X PCS/PMA or SGMII
  • All General ES silicon users must update to ISE 13.4 software and use the 1000BASE-X PCS/PMA or SGMII v11.2 release
  • (Xilinx Answer 45677) LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.2 - Release Notes and Known Issues for ISE Design Suite 13.4
• Tri-Mode Ethernet MAC
  
  • (Xilinx Answer 45707) LogiCORE Tri-Mode Ethernet MAC v5.2 - Release Notes and Known Issues for ISE Design Suite 13.4

Other Important Items:

• (Xilinx Answer 45360)Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon

Revision History

09/24/2012 - Minor update; no change to content
02/23/2012 - Updated IP Requirements and IP Known Issues sections
01/18/2012 - Added Answer Record 45870
01/11/2012 - Initial Release

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