Simulation should be used to calculate the latency with the target traffic pattern. Latency to an open and un-opened bank will vary slightly.
General read latency can be measured withrefresh, zqcalib, and periodic reads disabled. Worst case read latency should have these items included.
Additional InformationThe additionalnumber of fabric clock cycles required for switching from a read to write command can sometimes be affected by all the Bank Machines used. Increasing the number of Bank Machines can sometimes improve efficiency and turnaround times. For more information on the design's usage of Bank Machines and how to change the number of Bank Machines, please see
(Xilinx Answer 36505).
For higher frequency designs, a 4:1 memory to FPGA logic interface clock ratio is used which means for every fabric clock cyclefour DRAM clock cycles will occur. Using 2:1 mode at slower frequencies can sometimes reduce the turnaround latency by reducing the number of DRAM clock cycles that occur for every fabric clock cycle.