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  3. AR# 4556: M1.5 Constraints Editor Software Update Available on web site
  4. AR# 45563: IBERT Design Assistant - How to Use the Super Clock Module

AR# 45563

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IBERT Design Assistant - How to Use the Super Clock Module

描述

The following answer record discusses how to use the Super Clock Module that is available on some GT characterization boards such as the ML623.

Note: This Answer Record is a part of the Xilinx ChipScope Solution Center (Xilinx Answer 45310). The Xilinx ChipScope Solution Center is available to address all questions related to the ChipScope tool. Whether you are starting a new design with the ChipScope tool or troubleshooting a problem, use the ChipScope Solution Center to guide you to the right information.

解决方案

The super clock module is an add on board with programmable clock functionality that can provide a large selection of clock frequencies for use as a reference clock for transceivers. There are currently 2 different types of super clock modules available:

  1. XGI SuperClock Module
  2. SuperClock-2 Module

XGI SuperClock Module

The XGI SuperClock Module connects to a ML52x and ML42x GT characterization boards using a Xilinx Generic Interface connector (XGI). The output clock frequencies are selected using a dip switch to set the M/D values. To learn more information on how to use this board, please visit the XGI SuperClock Module Users guide:

UG091 - Xilinx Generic Interface (XGI) SuperClock Module User Guide

SuperClock-2 Module

The SuperClock-2 Module connects to various GT characterization boards (including the ML628, ML623, and SP623) using a QSH host interface connector. The SuperClock-2 Module is much more flexible than the previous generation and uses a I2C interface to configure the frequency of the output clocks.

The ML628, ML623, SP623, and KC724 development boards include an IBERT reference design (a ready made bit file) that includes a VIO core that controls the I2C interface to configure the output clocks for your needs.

To use the SuperClock-2 Module, you will need the bit file that comes with the IBERT reference design for your targeted development board

  1. Open ChipScope Analyzer and open the project file (.prj) that came with the IBERT reference design
  2. Configure the design with the bitstream that came in the IBERT reference design
  3. The VIO console should be open after configuration completes
  4. Consult the table at the bottom of the page to determine the address necessary to target the frequency desired on the outputs
  5. Enter in the address you determined from step 4 into the Si5368 Rom Addr field. Verify that the Si6368 ROM Freq (MHz) value changed to the frequency desired
  6. Click on the pulse button next to Si5368 Start
  7. Verify that the Si5368 Done LED has transitioned

As long as the board is not powered off, the SuperClock-2 module will continue to operate at the desired frequency. Configuring the part will not change the state of the outputs for the SuperClock-2 Module. This means that if it is desired to use a custom IBERT core, you can first configure with the IBERT reference design to start the clock at the desired frequency, then configure with thecustom IBERT design without losing the SuperClock-2 Module operation.

For more information on the SuperClock-2 Module, refer to the SuperClock-2 Module User Guide:

UG770 - HW-CLK-101-SCLK2 SuperClock-2 Module User Guide

SuperClock-2 address/frequency table

Addr Protocol Freq
32 OC-48 19.44
6 CPRI 61.44
18 GigE 62.50
63 Generic 66.67
11 Display Port 67.50
52 SDI 74.25
48 SATA 75.00
28 OBSAI 76.80
33 OC-48 77.76
59 XAUI 78.13
12 Display Port 81.00
1 Aurora 81.25
45 PCIe 100.00
15 Fibrechannel 106.25
7 CPRI 122.88
19 GigE 125.00
46 PCIe 125.00
23 Interlaken 132.81
64 Generic 133.33
13 Display Port 135.00
53 SDI 148.50
49 SATA 150.00
8 CPRI 153.63
29 OBSAI 153.60
34 OC-48 155.52
60 XAUI 156.25
0 100GE/40GE/10GE 161.13
14 Display Port 162.00
2 Aurora 162.50
37 OTU-1 166.63
65 Generic 166.67
56 SMPTE435M 167.06
41 OTU-2 167.33
43 OTU-3 168.05
5 CEI11 173.37
44 OTU-4 174.69
22 GPON 187.50
24 Interlaken 195.31
71 Generic 205.00
72 Generic 210.00
16 Fibrechannel 212.50
73 Generic 215.00
74 Generic 220.00
75 Generic 225.00
76 Generic 230.00
77 Generic 235.00
78 Generic 240.00
79 Generic 245.00
9 CPRI 245.76
20 GigE 250.00
47 PCIe 250.00
80 Generic 250.00
81 Generic 255.00
82 Generic 260.00
83 Generic 265.00
25 Interlaken 265.63
66 Generic 266.67
84 Generic 270.00
85 Generic 275.00
86 Generic 280.00
87 Generic 285.00
88 Generic 290.00
89 Generic 295.00
54 SDI 297.00
50 SATA 300.00
90 Generic 300.00
91 Generic 305.00
30 OBSAI 307.20
92 Generic 310.00
35 OC-48 311.04
61 XAUI 312.50
93 Generic 315.00
94 Generic 320.00
3 Aurora 325.00
95 Generic 325.00
96 Generic 330.00
38 OTU-1 333.26
67 Generic 333.33
57 SMPTE435M 334.13
97 Generic 335.00
98 Generic 340.00
99 Generic 345.00
100 Generic 350.00
101 Generic 355.00
102 Generic 360.00
103 Generic 365.00
104 Generic 370.00
105 Generic 375.00
106 Generic 380.00
107 Generic 385.00
108 Generic 390.00
26 Interlaken 390.63
109 Generic 395.00
110 Generic 400.00
111 Generic 405.00
112 Generic 410.00
113 Generic 415.00
114 Generic 420.00
17 Fibrechannel 425.00
115 Generic 425.00
116 Generic 430.00
117 Generic 435.00
118 Generic 440.00
119 Generic 445.00
120 Generic 450.00
121 Generic 455.00
122 Generic 460.00
123 Generic 465.00
124 Generic 470.00
125 Generic 475.00
126 Generic 480.00
127 Generic 485.00
10 CPRI 491.52
21 GigE 500.00
27 Interlaken 531.25
68 Generic 533.33
55 SDI 594.00
51 SATA 600.00
31 OBSAI 614.40
36 OC-48 622.08
62 XAUI 625.00
69 Generic 644.00
4 Aurora 650.00
39 OTU-1 666.51
70 Generic 666.67
40 OTU-1 666.75
58 SMPTE435M 668.25
42 OTU-2 669.31

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45310 Xilinx ChipScope Solution Center N/A N/A
43390 Kintex-7 FPGA KC724 Characterization Kit - Known Issues and Release Notes Master Answer Record N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
45562 IBERT Design Assistant - Using IBERT on Xilinx Development Boards (ML605, KC705, and et cetera) N/A N/A
AR# 45563
日期 01/30/2013
状态 Active
Type 综合文章
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