There is an issue with the DivGen 4.0 block Latency field. The workaround is to run simulation to determine the correct latency value.
For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
29595 | Xilinx DSP Tools, System Generator for DSP, and AccelDSP Synthesis Tool - Release Notes and Known Issues | N/A | N/A |
AR# 45516 | |
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日期 | 05/20/2012 |
状态 | Active |
Type | 已知问题 |
Tools |