2. 技术支持
  3. AR# 4443: FPGA Express 2.0 (Foundation 1.5): Instantiation of output cell with non-LVTTL voltage standard crashes Express

AR# 4443

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FPGA Express 2.0 (Foundation 1.5): Instantiation of output cell with non-LVTTL voltage standard crashes Express

描述

Keywords: Virtex, optimize, Voltage standard, I/O standard, AGP, CTT, GTL,
GTL+, GTLP, HSTL_I, HSTL_III, HSTL_IV, LVCMOS2, PCI33_3, PCI33_5,
PCI66_3, SSTL3_I, SSTL2_II, SSTL3_I, SSTL3_II

Urgency: Standard

General Description:

If you are targeting a Virtex design, and you have instantiated an output cell
with a non-LVTTL voltage standard, Foundation Express v2.1.2 will produce
an error in the optimization phase of synthesis.

Foundation Express 1.5 will report during optimize:

Internal Error: Invalid value '' for attribute
'pmap_slew' on ...... (FE-INTERNAL-padmap-2).

解决方案

This issue has been resolved with Foundation Express 2.1.3.
Please upgrade to Foundation F1.5i or newer.
AR# 4443
日期 08/31/2001
状态 Archive
Type ??????
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