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  3. AR# 43706: AXI Bridge for PCI Express - How to connect the axi_aclk and axi_ctl_aclk Ports

AR# 43706

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AXI Bridge for PCI Express - How to connect the axi_aclk and axi_ctl_aclk Ports

描述

The ports tab of the System Assembly View shows the axi_aclk and axi_ctl_aclk as inputs to the three AXI interconnect ports. What clocks should drive these input clocks?

解决方案

The axi_aclk and axi_ctl_aclkports should be connected to the axi_aclk_out and axi_ctl_aclk_out clocks, respectively. This will prevent any transferring of clock domains within the core.

Release History
11/28/2011 - Title update
08/19/2011 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44972 AXI Bridge for PCI Express FAQ N/A N/A
AR# 43706
日期 01/23/2013
状态 Active
Type 综合文章
IP
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