AR# 43667

描述

For optimal performance and maximum timing margin, the DQS strobe edges must be centered in the Read Data capture window with respect to the input capture flip-flop. Phase 2 of calibration is responsible for this DQS centering operation.

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解决方案

The DDR memory device output pins transmit the Read Data (DQ) and DQS strobes edge-aligned to the FPGA input pins as shown in Figure 4-3. For reliable operation, the DQS strobe must be delayed with respect to the DQ bits so that it captures the Read Data away from the transition region of the data bus.

During this phase, the tap delay count of the IDELAY block in the DQS strobe input path is incremented to shift the internal DQS signal at the capture flip-flop into the center of what will become the Read Data capture window as shown in Figure 4-3.

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