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  3. AR# 4365: 4.2i Foundation HDL Editor - I am unable to synthesize a top-level VHDL or Verilog file from HDL Editor
  4. AR# 43655: Virtex-6 FPGA Broadcast Connectivity Kit - FMC card reference clock from Si5324 device

AR# 43655

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Virtex-6 FPGA Broadcast Connectivity Kit - FMC card reference clock from Si5324 device

描述

On the Virtex-6 FPGA Broadcast Connectivity Kit FPGA Broadcast Mezzanine Card, the Si5324 device primarily provides a reference clock to the serial transceivers on the carrier board.

What codes are used on Si5324_clkin_sel to select the Si5324 clock input source?

解决方案

In the current build of the FPGA, codes 00, 01, and 11 can be used for the Si5324_clkin_sel input port.

Code 00 connects the 27 MHz XO to the Si5324.

Code 01 also connects the 27 MHz XO to the Si5324.

Code 11 connects the external video sync signal to the clock input of the Si5324. 

This mode has been used to implement genlock for Spartan-6 SDI demos (see XAPP1076).

Code 10 is not a valid code for use with the Si5324_clkin_sel input port on this mezzanine card.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
43656 Virtex-6 FPGA Broadcast Connectivity Kit - Known Issues and Release Notes Master Answer Record N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
43656 Virtex-6 FPGA Broadcast Connectivity Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 43655
日期 10/01/2014
状态 Active
Type 综合文章
Boards & Kits
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