Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).
NOTE: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
The ISE Design Suite13.2 v1.1 Rev 1 core allows you to generate a7 Series Integrated Block Wrapper for PCI Express for some devices that are not supported.
Currently, theCORE Generator softwarestill allows the core customization and generation for the Virtex-7 devices listed below. These devices do not contain a valid Generation 2 block for PCI Express, rather these devices contain a Generation 3 block. The Generation 3 block will be supported in a future wrapper release. The next update to the core will not allow the core to be generated when these devices are targeted.
The following three Kintex devices contain a valid block, but are not available in this release. However,you can contact Xilinx Support to obtain a UCF file for these devices.
Revision History
12/06/2011 - Added version resolved reference to Answer Record 40469
07/06/2011 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 40469 | 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
| AR# 42873 | |
|---|---|
| 日期 | 05/20/2012 |
| 状态 | Archive |
| Type | 已知问题 |
| 器件 | |