2. 技术支持
  3. AR# 4283: F1.4 Simulator: Simulating FPGA Express Netlist returns Warning 9218: unknown pin name
  4. AR# 42838: 7 Series Integrated Block for PCI Express - A Version 1.1 Core Does Not Implement in ISE Design Suite 13.2 Due to Port Changes on GTXE2_COMMON

AR# 42838

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7 Series Integrated Block for PCI Express - A Version 1.1 Core Does Not Implement in ISE Design Suite 13.2 Due to Port Changes on GTXE2_COMMON

描述

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

The core fails to implement in the ISE Design Suite13.2 due to changes on the underlying GTXE2_COMMON module. This module is instantiated as part of the GTX wrapper by the 7 Series Integrated Block Wrapper.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

解决方案

To fix this problem, generate a new core after installing the ISE Design Suite13.2. The ISE Design Suite13.2 contains v1.1 Rev 1 of the 7 Series Integrated Block Wrapper for PCI Express. See(Xilinx Answer 42517)for more information about v1.1 Rev 1.

Revision History
12/06/2011 - Added version resolved reference to AR 40469
10/21/2011 - Added link to release notes AR.
07/06/2011 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
42615 Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 Software N/A N/A
42517 Design Advisory for the 7 Series Integrated Block Wrapper for PCI Express - Port Changes in v1.1 rev 1 to be released in ISE 13.2 N/A N/A
AR# 42838
日期 05/20/2012
状态 Active
Type 已知问题
器件
Tools
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