2. 技术支持
  3. AR# 4267: F1.5 Project Archive: Archive may take a few minutes to begin on Windows NT
  4. AR# 42672: LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.1, 7 Series Transceiver Wrapper - GTX Port Name Changes in ISE 13.2 Software

AR# 42672

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LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.1, 7 Series Transceiver Wrapper - GTX Port Name Changes in ISE 13.2 Software

描述

Customers using the Ethernet 1000BASE-X PCS/PMA or SGMII v11.1 core (released in ISE13.1 software) should be aware that the port list in 7 Series FPGAs Transceivers has changed (released in the ISE 13.2 software). For simulation or implementation in the 13.2 software, users need to update their instantiations to account for these port changes. For more information on the change, see (Xilinx Answer 42615).

解决方案

To work aroundthis issue, you must change the ports of GTXE2 module instantiation.

GTXE2_CHANNEL Instantiation

In the \example_design\transceiver\gtxwizard_gt.v/vhd file:

Change:

'CPLL_RXOUT_DIV'

To:

'RXOUT_DIV'

and...

Change:

'CPLL_TXOUT_DIV'
To:

'TXOUT_DIV'

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
42615 Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 Software N/A N/A
AR# 42672
日期 12/15/2012
状态 Archive
Type 综合文章
IP
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