AR# 42626

描述

解决方案

To manage this issue, there are two changes required to the GTXE2 modules.

GTXE2_COMMON Module

Note: These changes only apply to cores that select 9.830 Gbps.

1. Go to the v7_gtwizard.vhd file in the example_design/gtx_and_clocks/gtx directory.

2. Change the following lines in the v7_gtwizard.vhd file:

Change:

BGBYPASS=> tied_to_ground_i,
BGMONITOREN=> tied_to_ground_i,

To:

BGBYPASSB => tied_to_vcc_i,
BGMONITORENB=> tied_to_vcc_i,

GTXE2_CHANNEL Module

Note: These changes apply to cores that select any line rate.

1. Go to the v7_gtwizard_gt.vhd file in the example_design/gtx_and_clocks/gtx directory.

2. Change the following lines in the v7_gtwizard_gt.vhd file:

Change:

'CPLL_RXOUT_DIV'

To:

'RXOUT_DIV'

Change:

'CPLL_TXOUT_DIV'

To:

'TXOUT_DIV'

For Release Notes and Known Issues for the LogiCORE CPRI, please see (Xilinx Answer 36969).

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