AR# 40779

描述

The Memory Controller drives the ODT, CKE, and RESET signals during normal operation and LOW during initialization.

However, a pull-down with a 4.7 KOhm resistor connected to GND is still required to adhere to the DDR, DDR2 and DDR3 Memory Standards.

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解决方案

Based off of the Power-Up Initialization Sequence defined by the DDR3 Spec, RESET# is recommended to be Low right at power On. 

To guarantee this occurs while the FPGA is being configured (before it can drive RESET "Low"), the pull-down to GND is recommended. 

Based off of the Power-Up Initialization Sequence defined by the DDR2 Spec, CKE and ODT should be maintained at a LOW state while applying power.

To guarantee this occurs while the FPGA is being configured (before it can drive CKE and ODT "Low"), the pull-down to GND is required. 

Based off of the Power-Up Initialization Sequence defined by the DDR Spec, CKE should be maintained at a LOW state while applying power. 

To guarantee this occurs while the FPGA is being configured (before it can drive CKE  "Low"), the pull-down to GND is required. 

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