What is a prefetchable bit?
What is the implication of not using this bit correctly?
NOTE: This answer record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.
Traditionally, prefetchabilitymeans to fetch memory beforehand into a small buffer so that the read operations become faster. For example, if you have two PCI buses connected by a bridge, if a host in primary bus has to access memory in the secondary bus, then the bridge would fetch data from the memory and store it in the bridge buffer. The host can then periodically access it and it would be much faster as well.
However, the memory has to be prefetchable. If the memory is not prefetchable, once the data is loaded into the buffer of the bridge, data will be lost from the memory. If the host cannot collect data from the bridge, then the data is lost forever. If the memory is prefetchable, there is no risk of data lost.
Revision History
1/24/2012 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 34538 | Xilinx Solution Center for PCI Express - Design Assistant | N/A | N/A |