2. 技术支持
  3. AR# 3965: V1.5, V1.4.0 CORE Generator - COREGen may create VHX, XNF(v1.4)/EDN(v1.5) and XSF output files when not directed to do so.
  4. AR# 39656: Viretx-6 FPGA Integrated Block for PCI Express - Clock net TxOutClk_bufg is not constrained

AR# 39656

|

Viretx-6 FPGA Integrated Block for PCI Express - Clock net TxOutClk_bufg is not constrained

描述

Version Found: v2.2
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

An unconstrained path analysis with the Virtex-6 FPGA Integrated Block Wrapper for PCI Express shows clock "inst_pci/core_i/TxOutClk_bufg" is not constrained.

解决方案

This is due to an issue with the ISE software not propagating the period constraint through the GTP onto the GTP TXOUCLK and impacts all core versions.

In order to fix this issue, add following constraint into your UCF file:

NET "core_i/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG";
TIMESPEC "TS_TXOUTCLKBUFG" = PERIOD "TXOUTCLKBUFG" [100 125 250]MHz HIGH 50 %

Use the frequency that matches your input reference clock as selected in thewrapper customization process.

Note that the UCF already constrains the outputs of the MMCM to the appropriate frequencies.

Revision History:
01/18/2012 - Updated; added reference to 45723
12/15/2010- Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
39353 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2 N/A N/A
37936 Virtex-6 FPGA Integrated Block Wrapper v1.6 for PCI Express - Release Notes and Known Issues N/A N/A
AR# 39656
日期 05/20/2012
状态 Archive
Type 已知问题
器件 More Less
IP
People Also Viewed