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  3. AR# 38242: Spartan-6 GTP Transceiver: Latency tables based on blocks used

AR# 38242

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Spartan-6 GTP Transceiver: Latency tables based on blocks used

描述

This Answer Record contains the latency tables for theSpartan-6 FPGA Transceiver, similar to those available in the Virtex-5 FPGA GTP Transceiver User's Guide. These table will be included in theSpartan-6 FPGA GTPTransceiver User's Guide in a future release.

解决方案

Transmiter Latency:

Block

Number
Block Name
Spartan-6 GTP - TX Latency (TXUSRCLK)



FPGA TX Interface
TXDATAWIDTH = 0
TXDATAWIDTH = 1
TXDATAWIDTH = 2

1 cycle
2 cycles
4 cycles



8B/10B Encoder
TXENC8B10BUSE = 0
TXENC8B10BUSE = 1

0 cycles
1 cycle



TX Buffer
TX_BUFFER_USE = FALSE
TX_BUFFER_USE = TRUE

1 cycles

2.5-3.5 cycles



PMA
1.5 cycle



PCS Interface
1 cycle

Total Latency
Maximum
Minimum

11 cycles
4.5 cycles



Receiver Latency:

Block

Number
Block Name
Spartan-6 GTP - RX Latency (RXUSRCLK)



FPGA RX Interface
RXDATAWIDTH = 0
RXDATAWIDTH = 1
RXDATAWIDTH = 2

2 cycle
3 cycles
5 cycles



Comma Detect
RXCOMMADETUSE = 0
RXCOMMADETUSE = 1



1 cycle
2-4 cycles



8B/10B Decoder
RXDEC8B10BUSE = 0
RXDEC8B10BUSE = 1

0 cycles
1 cycle



RX Buffer
RX_BUFFER_USE = FALSE
RX_BUFFER_USE = TRUE

2 cycles

1.5-2.5 cycles + CLK_COR_MIN_LAT



PMA
6 cycles +/- 1UI



PCS Interface
1 cycle

Total Latency
Maximum
Minimum

19.5 + CLK_COR_MIN_LAT cycles
12 cycles
AR# 38242
日期 12/15/2012
状态 Active
Type 综合文章
器件
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