2. 技术支持
  3. AR# 3663: Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R
  4. AR# 36633: Design Assistant for PCI Express - How can I know the values of the BARs after configuration?

AR# 36633

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Design Assistant for PCI Express - How can I know the values of the BARs after configuration?

描述

How can I check the values of the BARs after configuration?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

解决方案

Coming out of reset the BAR registers will contain all zeroes in bits 31:4 of a memory BAR and bits 31:2 of an I/O BAR. The lower bits in each case have special meaning and may be one or zero depending on the BAR configuration. See Chapter 6 of the PCI Local Bus Specification for more information on how BARs work..

After the link is trained and the BIOS has enumerated and configured the devices, you can view the starting address in each of the endpoint's BARs. There are mainly two ways to do this.

In hardware, use a tool such as PCITree or lspci to read the contents of the Link Status register. For more information about these types of software tools see (Xilinx Answer 34806) The BARs are located at configuration address offsets 0x10 to 0x24.

You can also use the core's configuration access port to read the contents of the BAR registers. See the core's user guide for information on how to use this port. See (Xilinx Answer 35920) to help locate the correct User Guide.

Generally, you do not really need to know this information for normal operation of your design. The core does all the BAR decoding so it will inform the user app if a BAR has been hit and the TLP packet contains the address which can be treated as an offset from zero.



Revision History
08/13/2010 - Initial Release

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35920 Xilinx Solution Center for PCI Express - Documentation N/A N/A
34806 Design Assistant for PCI Express - Software that Displays PCI Express Devices In System N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 36633
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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