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  3. AR# 36008: Virtex-6 FPGA Integrated Block Wrapper for PCI Express - The v1.3 and v1.3 rev 1 Core is not linking up reliably on ES (engineering sample) silicon using ISE 12.1 and ISE 11.5 or later software

AR# 36008

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Virtex-6 FPGA Integrated Block Wrapper for PCI Express - The v1.3 and v1.3 rev 1 Core is not linking up reliably on ES (engineering sample) silicon using ISE 12.1 and ISE 11.5 or later software

描述

Due to the automatic insertion of the MMCM calibration block that occurs in ISE11.5 and ISE 12.1 tools, the v1.3 or v1.3 rev 1 core might notreliably link up. This could occur on the ML605 board as well as your own board.

解决方案

This issue is fixed in the v1.3 rev 2 patch. Refer to (Xilinx Answer 34279) for the patch.

Revision History
08/10/2010 - Referred to AR 34279.
07/01/2010 - Added v1.3 rev 2 information
06/08/2010 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
33276 Virtex-6 FPGA Integrated Block Wrapper v1.3, v1.3 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33276 Virtex-6 FPGA Integrated Block Wrapper v1.3, v1.3 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 36008
日期 05/20/2012
状态 Archive
Type 已知问题
器件
Tools
IP
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