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  3. AR# 35291: MIG v3.4 - Virtex-4 - RLDRAMII - During simulation of the VHDL design iteration limit error occurs

AR# 35291

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MIG v3.4 - Virtex-4 - RLDRAMII - During simulation of the VHDL design iteration limit error occurs

描述

During simulation of the VHDL Virtex-4 FPGA RLDRAM II design the following error occurs:

   ** Error: (vsim-3601) Iteration limit reached at time 275026350 ps.
   # Executing ONERROR command at macro ./sim.do line 137


解决方案


This is due to a known issue with the Virtex-4 FPGA VHDL RLDRAMII design.

This issue does not occur with the Verilog design. 

This issue is resolved in the next release of MIG v3.5 due out in ISE Design Suite 12.2.

To work around this issue until then, constant delay parameters can be changed in sim_tb_top.vhd from "0.00 ns" to "0.01 ns".

Existing code:
  

   constant      TPROP_PCB_CTRL     : time := 0.00 ns; --CTRL delay value
   constant      TPROP_PCB_QK       : time := 0.00 ns; --QK delay value
   constant      TPROP_PCB_DATA     : time := 0.00 ns; --DATA delay value
   constant      TPROP_PCB_DATA_RD  : time := 0.00 ns; --READ DATA delay value



Modify the parameters as follows:
  

   constant      TPROP_PCB_CTRL     : time := 0.01 ns; --CTRL delay value
   constant      TPROP_PCB_QK       : time := 0.01 ns; --QK delay value
   constant      TPROP_PCB_DATA     : time := 0.01 ns; --DATA delay value
   constant      TPROP_PCB_DATA_RD  : time := 0.01 ns; --READ DATA delay value

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 35291
日期 08/12/2014
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Type 综合文章
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