RAMB16 Primitive | RAMB8 Primitive | |
Address Collision | When both ports are enabled (ENA and ENB =1 ), not using the same clock on both ports (CLKA CLKB), the phase offset between clocks can never be between 100 ps and 3 ns (or the next clock edge) and one of the following: 1) Both port widths are 18 and under: A13-A6,A4 are the same on both ports 2) The port width is 36 on either or both ports: A13-A7, A5 are the same on both ports. |
When both ports are enabled (ENA and ENB = 1) and not using the same clock on both ports (CLKA CLKB) and A12-A6, A4 are the same on both ports |
No Address Collision | When either port is disabled (ENA or ENB = 0), using the same clock on both ports (CLKA == CLKB), the phase offset between clocks is never between 100 ps and 3 ns (or the next clock edge) or one of the addresses in the following cases is always different for the two ports 1) Both port widths are 18 or under: A13-A6,A4 2) The port width is 36 on either or both ports: A13-A7,A5 |
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