AR# 34392

描述

This section of the MIG Design Assistant focuses on the efficiency of the 7 series and Virtex-6 FPGA DDR3/DDR2 controller. You will find information related to your specific question below.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Reordering Efficiency

The 7 series and Virtex-6 FPGADDR3/DDR2 design includes a highly efficient controller with reordering logic that it provides. This logic reorders received requests to optimize data throughput and latency. The reordering logic and controller are designed to transfer data efficiently for nearly any traffic pattern. Please review the Xcell article noted below for more details. The efficiency gains in the Virtex-6 controller over previous architectures is substantial.

The efficiency of the controller is highly dependent on the address/traffic pattern in use. To determine the efficiency for your specific application, it is important to simulate the design with the application's address/traffic pattern. It is possible to increase efficiency by modifying the number of bank machines used in the design. Changing the number of bank machines and re-simulating will show any improvements with the target address/traffic pattern.

For a complete description of how Reordering works, refer to the "DDR2 and DDR3 SDRAM Memory Interface Solution" > "Core Architecture" > "Memory Controller" > "Reorder" section in the 7 Series and Virtex-6 FPGA Memory Interface Solutions User Guides UG586 and UG406.

Enabling/Disabling Reordering Logic

Reordering is used by default but can be turned off and controlled by configuring the ORDERING parameter to "NORM" or "STRICT". "NORM" enables the reordering algorithm in the memory controller while "STRICT" disables reordering. This ORDERING option can be set in the MIG tool. For more information on using the ORDERING parameter, refer to the "DDR2 and DDR3 SDRAM Memory Interface Solution" > "Customizing the Core" section in the 7 Series and Virtex-6 FPGA Memory Interface Solutions User Guides UG586 and UG406.

Additional Information

• XCELL Article - Improving DDR SDRAM Efficiency with a Reordering Controller
• (Xilinx Answer 36719) Memory controller efficiency and possible improvements
• (Xilinx Answer 36752) Read/Write with Auto-Precharge
• (Xilinx Answer 36505) Bank Machines
• (Xilinx Answer 42977) MIG Virtex-6 DDR3 - Efficiency at BC4 (Burst Chop 4) mode

Revision History
09/18/2012 -Minor updates
02/15/2011 - Updated XCELL article link

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