In Virtex-6 FPGA instances of the 10-Gigabit Ethernet MAC v9.3 core, the MMCM parameter values used in the example design will result in a MMCM VCO frequency that is below the newly specified minimum.
This will result in DRC failures in the next release of the ISE Design Suite software.
For more information on the MMCM, see (Xilinx Answer 33849).
Depending on how the core was configured at generation time, the MMCM instances could appear in one or two locations in the example design.
Each of the MMCM parameter values should be changed as follows:
CLKFBOUT_MULT_F: from 3.0 to 6.0
CLKOUT0_DIVIDE_F: from 3.0 to 6.0
CLKOUT1_DIVIDE: from 3 to 6
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 33304 | LogiCORE IP 10-Gigabit Ethernet MAC v9.3 and v9.3 rev1 - Release Notes and Known Issues for ISE 11.3 and ISE 11.5 | N/A | N/A |
| 34019 | ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack | N/A | N/A |
| 33849 | Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 33304 | LogiCORE IP 10-Gigabit Ethernet MAC v9.3 and v9.3 rev1 - Release Notes and Known Issues for ISE 11.3 and ISE 11.5 | N/A | N/A |
| 34019 | ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack | N/A | N/A |